Field of the Invention
The present invention relates to a multilayer ceramic capacitor.
Description of the Related Art
In general, a multilayer ceramic capacitor has a capacitor body shaped roughly as a rectangular solid defined by length, width, and height, a first external electrode provided on one end of the capacitor body in the length direction, and a second external electrode provided on the other end of the capacitor body in the length direction. The capacitor body has a first protective part constituted by dielectrics, a capacitive part formed by multiple internal electrode layers stacked alternately with dielectric layers, and a second protective part constituted by dielectrics, all of which are arranged in layers in this order in the height direction. In addition, the multiple internal electrode layers included in the capacitive part are such that the edge, on the first external electrode side, of an odd-numbered layer from one end in the height direction is electrically connected to the first external electrode, while the edge, on the second external electrode side, of an even-numbered layer from one end in the height direction is electrically connected to the second external electrode.
In general, the aforementioned multilayer ceramic capacitor is mounted in a desired manner by connecting the bottom faces of the first external electrode and second external electrode in the height direction to two conductor pads on a circuit board, respectively, using solder. When voltage, especially alternating current voltage, is applied to the first external electrode and second external electrode through the respective conductor pads with the capacitor mounted this way, the capacitor body undergoes expansion/contraction based on electrostriction (primarily contraction that causes the capacitive part to contract in the length direction, and recovery from such contraction) and the stress accompanying this expansion/contraction is transmitted to the circuit board to induce vibration (primarily warping that causes the section between the conductor pads to form a concave, and recovery from such warping), and this vibration may lead to generation of sounds in audible frequency bands (between 20 Hz and 20 kHz).
As for the aforementioned sound generation (so-called “noise”), various countermeasures have been attempted, including known structures such as the multilayer ceramic capacitor 100 shown in FIG. 1 (refer to Patent Literature 1 listed later, for example). In FIG. 1, the numeral 101 represents a capacitor body, 102 represents a first external electrode, 103 represents a second external electrode, PP1 represents a first protective part, CP represents a capacitive part, PP2 represents a second protective part, 104 represents an internal electrode layer, 105 represents a dielectric layer, and the structural details are as described earlier. This multilayer ceramic capacitor 100 is structurally characterized in that the thickness of the second protective part PP2 is made greater than the thickness of the first protective part PP1 so as to shift the height-direction position of the capacitive part CP upward.
The multilayer ceramic capacitor 100 shown in FIG. 1 is mounted in a desired manner by connecting the bottom faces of the first external electrode 102 and second external electrode 103 in the height direction to two conductor pads on a circuit board, respectively, using solder. However, this multilayer ceramic capacitor 100 allows the capacitive part CP to separate upward from the respective conductor pads in a mounted state, which leads to an increase in ESL (equivalent series inductance) as the route of electrical current increases.
The aforementioned ESL has negative effects on signal transmissions in high-frequency ranges, specifically in high-frequency ranges of several hundred MHz or higher, and therefore when the multilayer ceramic capacitor 100 shown in FIG. 1 is used as a component of a high-frequency circuit, high-frequency signals are subject to higher transmission losses as they flow, which makes it difficult for the capacitor to demonstrate its intended capability.
[Patent Literature 1] Japanese Patent Laid-open No. 2013-251551